Introduction The rise in the high performance devices has made power as one of the most crucial constraints in the design cycle, along with performance and area. Technology advancements and on-chip temperature conditions inject reliability and variability issues in modern chips. This makes an analysis of power consumption more critical. Knowledge about power budget of the circuit is not only necessary in the design cycle, but also in manufacturing test of the circuit under test (CUT). The designer has to select a correct technique based on allowed power, area and performance specifications. For effective decision making at every design stage, analysis of maximum power demand by design under development is necessary. Along with design decisions, manufacturing test development also have to take maximum allowable power values into account. Violation of power budget during test the application can introduce delay faults which may not be present in normal operation. Thus power safety is required to avoid false failures and yield loss. Power consumption by circuit depends on the number of logic transitions at nets and physical parameters like capacitance values and supply voltage. However detailed analysis is computationally expensive and time consuming even for a small set of inputs. As explained earlier, power analysis is required almost every stage and is a repetitive process till final specifications are achieved. Thus it should be fast enough. Selection of few power hungry input patterns (PHP) which stimulates maximum logic in CUT is desirable to estimate maximum power demand. We propose a procedure to get a pair of power hungry inputs (V1,V2) which will extract maximum power from the source. Modern circuit designs with intricate and large number of basic design module like multiplexers, adders, memory elements, etc have to be targeted. Some of the modules can be deeply embedded in the design hierarchy and does not have easy access from primary input pins. These make PHP generation more challenging at gate level as it requires rigorous logic simulations or backtracking. However, module level input-output dependency is available at RTL level and can be utilized to find PHP quickly. If power behavior of basic design modules can be made available at RTL level, then the task can be made easier. Our work focuses on the generation of PHP in time efficient manner at RTL level of design such that total power consumption is maximized. The generated PHP will be used as input stimuli & detailed transistor level power analysis can be performed to estimate maximum power consumption by the CUT. This will enable designers to analyze power behavior under carefully generated input set than many number random inputs. Rest of the paper is organized as per following sections. Section II describes the related work proposed by the researchers. The basic approach of proposal is given in Section III. Section number IV and V elaborates on techniques, genetic algorithms and power model used in proposed method. Effectiveness with the results are reported in Section VI. VII concludes the work with possible future directions.
Related Work Most of the methods involve simulations performed on random data inputs. We emphasize on the generation of high power demanding hungry vectors PHP at RTL level to gain time benefit and use these power vectors to perform detailed analysis at a lower level to achieve accuracy. Some of the literature has named these vectors as Power Virus. However, generation of PHP at the higher abstraction level of design is not traversed much. Some of the techniques to get PHP are [1][2][3][4][5]. Due to the availability of structural information of cells (gate) connections in the design, it is comparatively easy to generate PHP relatively small circuits. One of the techniques is symbolic variable (ILP/SAT) based power estimation proposed by Rohini et al. [5]. Authors formulate an optimization problem to generate PHP vectors. This method can estimate total switching considering the final logic transition as well as glitches which occur as a result of non-zero gate delays. However, complexity increases tremendously as design size increases. One approach to generate power virus at behavior level is proposed by Najeeb et al.[6], ILOG based optimization problem is solved to get high power inputs. This approach is faster than gate level, however it is not applicable to sequential designs. Higher level designs can be seen as a collection of small design modules (or RTL component libraries) and data or control line connections between modules. Traditionally power estimation problem a higher level is primarily focused on the development of fast and accurate power models for RTL modules and simulations of large number of samples in inputs space. These abstract power models can be expressed in the form of equations or lookup tables by analyzing the empirical data from simulations or statistical analysis of CUT [7][9][10]. Increasing the accuracy and speed of model was a major aim so far such that maximum random input set can be simulated. However, interest has been developed towards further improvement of the simulation speed to cover most of the inputs space by emulating power behavior [11][12]. The contribution of proposed approach is the generation of effective input data set.